1. Basic steps of appearance inspection
The appearance inspection of MOS transistors mainly determines whether there is physical damage by visually observing their packaging, pins, surface condition, etc. Here are some key checkpoints.
1.1 Check if the packaging is complete
The packaging of MOS diodes usually adopts various forms such as TO-220, TO-247, SOT-23, etc. The integrity of the packaging is crucial for the normal operation of MOS transistors. Damaged or cracked packaging may cause damage to the internal structure of MOS transistors, affecting their functionality.
Cracks or fragments: If cracks or fragments appear on the packaging surface of MOS transistors, it may be due to excessive mechanical impact or high temperature overload, resulting in package rupture. Package damage not only affects its heat dissipation performance, but may also lead to electrical short circuits or open circuits, causing MOS transistors to malfunction.
Packaging expansion or deformation: High temperature or overcurrent may cause overheating inside the MOS transistor, resulting in packaging deformation or expansion. The deformed packaging may no longer be reliable and may cause internal circuit failures.
1.2 Check the surface condition
The surface of MOS transistor should be kept clean and free of foreign matter adhesion. Surface abnormalities may be external manifestations of thermal damage, current overload, or other faults occurring inside the MOS transistor.
Surface discoloration: Under normal circumstances, there should be no obvious discoloration or coking on the surface of MOS transistors. If there is a significant change in surface color, especially turning black or yellow, it usually indicates that it has experienced overheating or short circuit events and may have been damaged.
Burn or smoke marks: If there are burn or black burn marks on the surface of the MOS transistor, it may be due to overheating caused by overload, short circuit, or long-term high current operation, resulting in local damage.
1.3 Check the condition of the pins
The pins of a MOS transistor are a critical part of its connection to the circuit, and any damage or corrosion to the pins may cause the circuit to malfunction.
Pin corrosion or oxidation: Prolonged exposure to humid environments or high temperatures can cause corrosion or oxidation of MOS transistor pins, resulting in discoloration, blackening, or the appearance of green spots on the surface of the pins. Corrosion and oxidation can cause poor connections between pins and circuits, thereby affecting the operation of MOS transistors.
Pin bending or breakage: If the pin is bent, broken, or loose, it can cause poor electrical contact and even prevent normal connection to the circuit, and the damaged MOS transistor must be replaced.
2. Use auxiliary tools to further detect
In addition to visual inspection, using some simple tools can help us more accurately determine whether the MOS transistor is damaged.
2.1 Digital multimeter inspection
A multimeter is a commonly used tool for detecting the status of MOS transistors. When conducting digital multimeter testing, the main focus is on checking the switching characteristics of MOS transistors, including their conduction characteristics, breakdown voltage, etc.
Leakage current test: Use the diode gear of a multimeter to measure the leakage current of the MOS transistor. Under normal circumstances, the leakage current of MOS transistors should be very small. In the “diode mode” of the multimeter, check the resistance between the source and drain of the MOS transistor. If there is obvious current leakage, it indicates that the MOS transistor may have been damaged.
Gate voltage inspection: Determine the switching characteristics of MOS transistors by measuring the effect of gate voltage on the source. Under normal circumstances, the gate voltage of a MOS transistor needs to reach a certain threshold in order to conduct. If the gate voltage is inappropriate or the gate current is abnormal, there may be a problem with the MOS transistor.
2.2 Infrared thermal imaging detection
In high-power circuits, MOS transistors generate heat during operation. Through infrared thermography detection, we can identify whether MOS transistors are overheated, which is very helpful in determining whether they are damaged.
Uneven temperature or overheating: If abnormal temperature distribution of the MOS tube is detected through thermal imaging, especially if a certain part of the temperature is too high, it indicates that there may be a short circuit or overload inside the MOS tube, leading to overheating damage. At this point, it is necessary to replace the damaged MOS transistor.
2.3 Oscillator Test
For power MOS transistors, switching characteristics testing can be conducted using an external oscillator to check their switching frequency and response speed. If the switching frequency of the MOS transistor is too low or the response time is delayed, it may indicate that its internal structure has degraded or been damaged.
By checking the physical characteristics such as packaging integrity, surface condition, and pin connections, we can preliminarily identify the damage of MOS transistors. Although appearance inspection cannot completely replace electrical performance testing, it can help us quickly detect external damage and take timely measures to avoid the spread of faults.
]]>1. Basic steps of appearance inspection
The appearance inspection of MOS transistors mainly determines whether there is physical damage by visually observing their packaging, pins, surface condition, etc. Here are some key checkpoints.
1.1 Check if the packaging is complete
The packaging of MOS diodes usually adopts various forms such as TO-220, TO-247, SOT-23, etc. The integrity of the packaging is crucial for the normal operation of MOS transistors. Damaged or cracked packaging may cause damage to the internal structure of MOS transistors, affecting their functionality.
Cracks or fragments: If cracks or fragments appear on the packaging surface of MOS transistors, it may be due to excessive mechanical impact or high temperature overload, resulting in package rupture. Package damage not only affects its heat dissipation performance, but may also lead to electrical short circuits or open circuits, causing MOS transistors to malfunction.
Packaging expansion or deformation: High temperature or overcurrent may cause overheating inside the MOS transistor, resulting in packaging deformation or expansion. The deformed packaging may no longer be reliable and may cause internal circuit failures.
1.2 Check the surface condition
The surface of MOS transistor should be kept clean and free of foreign matter adhesion. Surface abnormalities may be external manifestations of thermal damage, current overload, or other faults occurring inside the MOS transistor.
Surface discoloration: Under normal circumstances, there should be no obvious discoloration or coking on the surface of MOS transistors. If there is a significant change in surface color, especially turning black or yellow, it usually indicates that it has experienced overheating or short circuit events and may have been damaged.
Burn or smoke marks: If there are burn or black burn marks on the surface of the MOS transistor, it may be due to overheating caused by overload, short circuit, or long-term high current operation, resulting in local damage.
1.3 Check the condition of the pins
The pins of a MOS transistor are a critical part of its connection to the circuit, and any damage or corrosion to the pins may cause the circuit to malfunction.
Pin corrosion or oxidation: Prolonged exposure to humid environments or high temperatures can cause corrosion or oxidation of MOS transistor pins, resulting in discoloration, blackening, or the appearance of green spots on the surface of the pins. Corrosion and oxidation can cause poor connections between pins and circuits, thereby affecting the operation of MOS transistors.
Pin bending or breakage: If the pin is bent, broken, or loose, it can cause poor electrical contact and even prevent normal connection to the circuit, and the damaged MOS transistor must be replaced.
2. Use auxiliary tools to further detect
In addition to visual inspection, using some simple tools can help us more accurately determine whether the MOS transistor is damaged.
2.1 Digital multimeter inspection
A multimeter is a commonly used tool for detecting the status of MOS transistors. When conducting digital multimeter testing, the main focus is on checking the switching characteristics of MOS transistors, including their conduction characteristics, breakdown voltage, etc.
Leakage current test: Use the diode gear of a multimeter to measure the leakage current of the MOS transistor. Under normal circumstances, the leakage current of MOS transistors should be very small. In the “diode mode” of the multimeter, check the resistance between the source and drain of the MOS transistor. If there is obvious current leakage, it indicates that the MOS transistor may have been damaged.
Gate voltage inspection: Determine the switching characteristics of MOS transistors by measuring the effect of gate voltage on the source. Under normal circumstances, the gate voltage of a MOS transistor needs to reach a certain threshold in order to conduct. If the gate voltage is inappropriate or the gate current is abnormal, there may be a problem with the MOS transistor.
2.2 Infrared thermal imaging detection
In high-power circuits, MOS transistors generate heat during operation. Through infrared thermography detection, we can identify whether MOS transistors are overheated, which is very helpful in determining whether they are damaged.
Uneven temperature or overheating: If abnormal temperature distribution of the MOS tube is detected through thermal imaging, especially if a certain part of the temperature is too high, it indicates that there may be a short circuit or overload inside the MOS tube, leading to overheating damage. At this point, it is necessary to replace the damaged MOS transistor.
2.3 Oscillator Test
For power MOS transistors, switching characteristics testing can be conducted using an external oscillator to check their switching frequency and response speed. If the switching frequency of the MOS transistor is too low or the response time is delayed, it may indicate that its internal structure has degraded or been damaged.
By checking the physical characteristics such as packaging integrity, surface condition, and pin connections, we can preliminarily identify the damage of MOS transistors. Although appearance inspection cannot completely replace electrical performance testing, it can help us quickly detect external damage and take timely measures to avoid the spread of faults.
]]>1、 Understand the structure of Schottky diodes
Unlike ordinary diodes, Schottky diodes are formed by metal semiconductor contacts and do not have traditional PN junctions. Its shell is usually made of plastic or ceramic material, and there are metal pins on the outside for circuit connection. The design characteristics of Schottky diodes result in lower voltage resistance, so special attention should be paid to external damage that may affect their stability during appearance inspection.
2、 Key points of appearance inspection
In appearance inspection, the quality of Schottky diodes can be judged from the following aspects:
1. Integrity and sealing of the shell
The shell of a Schottky diode is an important barrier that protects its internal structure. When observing the casing, carefully check for cracks, scratches, or damage. If cracks, notches, or other obvious damages are found, it may allow external moisture or dust to enter the inside of the diode, affecting its performance and even causing a short circuit. The color of the shell can also be one of the standards for testing. Some high-quality plastic packaging shells may have a relatively uniform black luster, while inferior materials may appear rough or gray.
2. Pin condition
Pin is a critical component that connects diodes and circuit boards. When checking the pins, pay attention to whether they are bright, free of oxidation or rust. The pins of Schottky diodes are usually coated with a layer of tin, which not only helps prevent oxidation but also improves solderability. Corrosion or oxidation can cause poor contact, thereby affecting electrical performance. If the pins are severely deformed, it may affect installation and conductivity, and should be replaced in a timely manner.
3. Clarity of Identification
The shell of Schottky diodes usually bears the model, specifications, and brand identification. These markings not only help identify the rated current and voltage parameters of diodes, but also prevent the mixing of diodes of different specifications. During testing, it should be ensured that the identification is clear, without blurring or detachment. Blurred identification diodes may be products with poor storage conditions or poor printing processes, and their quality is usually low, so they are not recommended for use.
4. Surface substances or unknown pollutants
During the inspection process, if oil stains, gel like substances, or other unknown substances are found on the surface of the Schottky diode casing, they should be taken seriously. High quality diode packaging should have good sealing properties, and the surface is usually clean and free of impurities. If there are unknown substances on the surface, it may be due to poor packaging causing internal material leakage, or the diode has been affected by adverse environmental factors. There may be issues with the internal stability of these diodes.
5. Observe the solder pads and coatings
High quality Schottky diodes have a uniform coating on their pins, which enhances conductivity and solderability. When observing the pins, it is possible to check whether the coating is complete and free from detachment. If the coating is incomplete or there is peeling, it indicates that the product has been adversely affected during manufacturing or storage, which can lead to a decrease in welding effectiveness and thus affect electrical performance.
3、 Other testing suggestions
Appearance inspection can help us screen out some obviously defective Schottky diodes, but it can only judge the appearance quality and cannot fully reflect the internal electrical performance. In practical use, it is recommended to combine the following testing methods to ensure that its performance meets the requirements:
1. Positive and reverse resistance test
Measure the forward and reverse resistance of a Schottky diode using the diode range of a multimeter. In forward resistance testing, the diode should display a certain low resistance value, while in reverse resistance testing, it should display infinity. If the measured forward resistance is large or the reverse resistance is not infinite, it may indicate that the diode is damaged internally.
2. Open circuit and short circuit detection
Check for short circuits or open circuits in the diode through a simple multimeter test. A short circuited diode can cause excessive current in a circuit, which can damage the entire circuit in severe cases, while an open circuit diode cannot achieve current rectification. If an open or short circuit is found in the Schottky diode, it should be replaced immediately.
3. Aging test
For application scenarios with high quality requirements, aging tests can be conducted to verify the stability of Schottky diodes in high temperature and high voltage environments. Aging testing can help us detect potential problems in advance and eliminate components that fail early, thereby ensuring the reliability of the product.
The appearance inspection of Schottky diodes is an important preliminary screening method. By carefully inspecting key points such as the casing, pins, markings, contaminants, and coating, it is possible to screen out some components with poor quality and reduce the risk of defective products entering the production line. However, it should be noted that appearance inspection can only judge the external quality and cannot completely replace electrical performance testing
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Stefan Rosinger, Senior Director of Product Management at Arm Terminal Business Unit, said, “We are currently in the midst of the AI revolution and have witnessed firsthand the rise of multimodal AI models. These models are capable of processing and understanding a variety of data types, including text, images, audio, video, and sensor data. However, due to the power and memory constraints of the hardware itself, as well as the complexity of processing multiple data types simultaneously, deploying these advanced multimodal models on end devices is facing significant challenges
Arm Kleidi is an ideal solution to address these challenges, providing seamless performance optimization for all AI inference workloads running on Arm CPUs. KleidiAI is a lightweight and high-performance open-source Arm routine designed specifically for AI acceleration. It has been integrated into the latest versions of mainstream end-to-end AI frameworks, including ExecutuTorch, Llama.cpp, LiteRT (via XNNPACK), and MediaPipe, allowing millions of developers to automatically achieve significant improvements in AI performance without the need for additional actions.
Accelerate the response time of end side multimodal AI use cases
Through the integration of KleidiAI and MNN, the Arm and MNN teams measured the acceleration performance of the Qwen2-VL-2B-Instruct model, and the results showed that its running and response speed were improved in key AI multimodal application scenarios on the end side. This improvement can bring a better user experience to many customer-centric applications under Alibaba.
The improvement in response speed for these use cases is due to a 57% increase in model pre filling (referring to the AI model processing prompt input before generating a response) performance and a 28% increase in decoding (referring to the process of generating text from the AI model after processing prompt words) performance. In addition, KleidiAI integration can further promote efficient processing of AI workloads on end devices by reducing the overall computational cost of multimodal workloads. Millions of developers who use popular AI frameworks, including MNN frameworks, to run applications and workloads can enjoy these performance and efficiency improvements in applications and workloads targeting edge devices.
Xu Dong, General Manager of Alibaba Cloud’s Tongyi Big Model Business, said, “We are very pleased to see the deep technical cooperation between Tongyi Qianwen Big Model and Arm KleidiAI and MNN teams. Through the integration and acceleration optimization of MNN end-to-end inference framework and Arm KleidiAI, we have successfully achieved a significant reduction in big model inference latency and a significant improvement in energy efficiency ratio. This groundbreaking collaboration not only fully validates the practical potential of big models in mobile devices, but also enables users to experience the inclusive value of next-generation AI at their fingertips. We look forward to the three parties continuing to work together, breaking through the boundaries of computing power through technological innovation, and jointly opening a new chapter in end-to-end intelligence
Jiang Xiaotang, the head of business technology MNN at Alibaba Taotian Group, said, “This deep technical integration between MNN inference framework and Arm KleidiAI has achieved a new breakthrough in end-to-end large model acceleration. Through our joint optimization of the underlying architecture, the end-to-end inference efficiency of the Tongyi large model has been significantly improved, successfully crossing the technological gap between limited computing power and complex AI capabilities. This achievement is not only the crystallization of the MNN team’s technological breakthroughs, but also a vivid interpretation of the power of cross-border collaboration. We look forward to continuing to work together to deeply cultivate the end-to-end computing ecosystem in the future, so that every mobile terminal can carry a smoother, more efficient, and more natural AI experience
KleidiAI integration demonstration at MWC
At this year’s Mobile World Congress (MWC), Arm showcased the results of this collaboration at the event booth (Hall 2, Booth I60), highlighting how models understand various combinations of visual and textual inputs and extract and explain the content in images. This demonstration was conducted on smartphones equipped with MediaTek Dimensity 9400 Mobile System on Chip (SoC), including the vivo X200 series.
A leap towards achieving multimodal AI experience
The integration of KleidiAI and the MNN framework supported by Alibaba’s Tongyi Qianwen model has successfully brought significant user experience improvements to multimodal AI workloads running on the Arm CPU side. These excellent experiences have now been applied to mobile devices, and many customer-oriented applications have also benefited from the various advantages brought by KleidiAI. Looking ahead, KleidiAI’s seamless optimization for AI workloads will continue to empower developers to provide more complex multimodal experiences on edge devices. This will lay the foundation for the next wave of intelligent computing and take an exciting step forward in the continuous evolution of AI.
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Automotive components have now been largely electrified, and the demand for motors and the number of motors integrated into cars are increasing. With the increasing number of driver ICs used in electric motors, people are more inclined to adopt high integration and miniaturized system solutions. In addition, some motor applications do not require speed control and only require driver ICs with simple functions and performance.
TB9103FTG provides optimized gate drive IC functionality and performance for DC brushed motors that do not require speed control, paving the way for more compact designs. It has a built-in charge pump circuit [4] that ensures the voltage required to power the external MOSFET of the driving motor. In addition, it also has gate monitoring function, which can automatically control the timing of gate signal output for high and low side external MOSFETs to prevent the generation of through current. At the same time, the IC also has a built-in sleep function, which can reduce power consumption during standby.
This new IC can be used as both a single channel H-bridge and a dual channel half bridge. In addition to serving as a motor driver IC, it can also be combined with external MOSFETs to replace mechanical relays and other mechanical switches, which helps achieve quieter operation and higher equipment reliability.

Application circuit example of H-bridge mode
TB9103FTG is packaged in VQFN24 with a size of 4.0 mm × 4.0 mm (typical value), which helps to reduce device size.
The reference design for the control circuit of a car mounted DC brushed motor using TB9103FTG has been released on Toshiba’s website.
In the future, Toshiba will continue to expand its product line of automotive motor driver ICs, contributing to the electrification and safety improvement of automotive equipment.
Application:
Onboard equipment
-Drivers for latch motors and locking motors used for electric rear doors and electric sliding doors; Drivers for motors used in car windows and electric seats, etc
Characteristic:
-Simplified functionality and performance contribute to miniaturization
-Small Package
-Low standby power consumption (built-in sleep function)
-Can be used as a gate driver IC for single channel H-bridge or dual channel half bridge
-Compliant with AEC-Q100 (Grade 1) standard
Main specifications:

Note:
[1] Gate driver IC: A driver IC that drives MOSFETs.
[2] Latch motor: a motor used in the system to keep the car doors closed.
[3] Locking motor: a motor used in conjunction with a key in the system to lock and unlock car doors to prevent criminal activity.
[4] Charge pump circuit: a circuit that uses capacitors and switches to boost voltage.
Shanghai, China, March 24, 2025- Cadence Electronics (NASDAQ: CDNS) announced today the expansion of its multi-year partnership with NVIDIA, with a focus on driving the development of accelerated computing and proxy AI. This cooperation aims to address key global technological challenges, promote innovative development in various industries, and achieve substantial breakthroughs.

Cadence drives technological innovation across multiple industries by integrating NVIDIA accelerated computing technology. Based on NVIDIA’s latest Blackwell architecture, Cadence? Series engineering and scientific solutions enable large-scale acceleration, enabling designers to tackle larger and more complex problems that were previously difficult to solve. The results of this collaboration are as follows:
The simulation time of computational fluid dynamics has been shortened by up to 80 times, from a few days to tens of minutes;
Cadence Spectre X Simulator accelerates up to 10 times;
The 3D-IC design and analysis of thermal, stress, and warpage can be accelerated up to 7 times.
Cadence Fidelity CFD platform utilizes Blackwell to solve the most complex fluid mechanics problems
Cadence utilizes the NVIDIA Blackwell platform to help solve a major challenge in computational fluid dynamics (CFD): simulating the entire aircraft in the most challenging parts of the flight envelope (during takeoff and landing). With the help of the Cadence Fidelity CFD platform, Cadence successfully ran simulations of billions of grid cells on NVIDIA GB200 GPU in less than 24 hours. Prior to this, the simulation process relied on a Top 500 CPU cluster with hundreds of thousands of cores and took several days to complete. Cadence will continue to utilize the limits of Blackwell test simulation to help the aerospace industry reduce wind tunnel testing frequency, lower costs, and accelerate the time to market process.
此外,Cadence 還與 NVIDIA 攜手開發(fā)面向電子系統(tǒng)設計以及科學應用的全棧代理式 AI 解決方案。此次合作將引入突破性代理技術(shù),將 Cadence JedAI 平臺與 NVIDIA 的 NeMo 生成式 AI 框架和新發(fā)布的 NVIDIA Llama Nemotron 推理模型相整合,提高設計生產(chǎn)力,例如:
智能對話式 AI 助手,可提高用戶生產(chǎn)力和創(chuàng)新能力;
基于底層設計資源和驗證代理的深度驗證推理;
利用設計代理,實現(xiàn)數(shù)字和定制電路的設計生成與優(yōu)化。
In addition, Cadence Molecular Sciences (OpenEye) is integrating NVIDIA BioNeMo NIM microservices with Cadence’s cloud native molecular design platform Orion? Integration. This collaboration aims to accelerate the innovation of drug development tools by combining excellent cloud AI and GPU technologies. Orion has breakthrough on-demand and reserved GPU access capabilities, which can help global scientists carry out large-scale complex computing and revolutionize therapeutic drug design. NIM microservices have extended Orion’s capabilities, as follows:
An AI model used for heavy head prediction of protein three-dimensional structure;
Small molecule generative AI;
A basic AI model for predicting antibody characteristics.
Cadence is utilizing NVIDIA’s advanced digital twin technology to accelerate the construction of AI infrastructure. Cadence is proud to be one of the first companies to adopt NVIDIA Omniverse Blueprint, a digital twin designed for AI factories. This collaboration has promoted consistent and accurate model creation, enabling the rapid development of digital twins in data centers. NVIDIA Omniverse Viewport、Cadence Allegro? X Design Platform and Cadence Reality? The integration of Digital Twin Platform enables designers to gain a fresh perspective and more precise insight into the entire electronic system design process. Downstream users can utilize data for analysis and use in areas such as device and BOM management, manufacturing interfaces, system level quality, and mechanical and industrial design. NVIDIA and Cadence are at the forefront of creating high-quality model ecosystems, opening the door for device manufacturers and data center companies to quickly and confidently create digital twin solutions.
Cadence is accelerating AI driven EDA and system design and analysis workloads on NVIDIA’s latest Grace Blackwell NVL72 platform. We can help deliver infrastructure AI and agent-based AI that meet current needs, and reshape the simulation foundation for physical AI and scientific AI. ”Dr. Anirudh Devgan, President and CEO of Cadence, stated. With these technological breakthroughs, we are able to complete large-scale complex system simulations that were previously difficult to achieve within hours, including some of the largest and most accurate whole machine simulations to date
Accelerated computing and agent-based AI are redefining innovation standards in various industries. ”NVIDIA founder and CEO Huang Renxun said. NVIDIA and Cadence work together to continuously break through technological boundaries, making significant progress in simulation, optimization, and design, helping to improve efficiency, shorten product time to market, and drive scientific exploration to new heights
]]>Faced with the surge of edge data, efficient data processing, low latency transmission, and intelligent and secure storage are becoming the focus of industry attention. The future computing architecture must not only provide stronger computing power, but also be more closely integrated with storage systems to ensure that AI models can run efficiently, while optimizing data management and access methods.
From the current development direction of AI technology, on the one hand, large models are evolving towards General Artificial Intelligence (AGI), exploring new directions such as multimodal and physical AI, and continuously challenging new limits of computing power. On the other hand, in order to promote the overall deployment of the big model, the industry began to move towards in-depth optimization and customization of vertical fields, so that the big model can go into thousands of industries and adapt to different scenarios such as mobile terminal, edge computing, cloud deployment, etc.
The launch of DeepSeek has had a profound impact on the global AI market: as an open and innovative technology, it not only demonstrates the optimization potential of AI in the training and inference process, but also greatly improves the efficiency of large-scale deployment, fully proving that the model can run stably in a lower cost and higher efficiency environment. This achievement is of great significance for promoting the large-scale application of AI in enterprise applications and edge computing.
Arm Computing Platform: Continuously Promoting AI Optimization Deployment from Cloud to End
In the early stages of AI development, data centers, as the core location for model training and initial inference, are facing unprecedented challenges. Traditional standard general-purpose chips are inadequate in handling computationally intensive AI workloads and cannot meet the urgent needs of the AI era for high performance, low power consumption, and flexible scalability. In this context, the Arm computing platform, with its advanced technological advantages, has opened up a new paradigm for the development of next-generation AI cloud infrastructure. From the Arm Neoverse Computing Subsystem (CSS), Arm Total Design ecosystem project to the Core System Architecture (CSA), Arm has made an integrated layout from technology to ecology. It not only provides efficient, flexible, and scalable solutions for AI data center workloads, but also helps partners focus on product differentiation and accelerates the product launch process.
AI reasoning is the key to unlocking value for AI, and it is rapidly expanding from the cloud to the edge, covering every corner of the world. In the field of edge AI, Arm continuously innovates with its unique advantages in technology and ecology, ensuring that the intelligent Internet of Things and consumer electronics ecosystem can perform optimal workloads at the right time and in the most suitable location.
In order to meet the increasing demand for AI workloads in edge AI, Arm recently released an edge AI computing platform centered around the new Armv9 ultra high energy efficiency CPU Cortex-A320 and Ethos-U85 AI accelerator with native support for Transformer networks. This platform achieves deep integration of CPU and AI accelerator. Compared to last year, the Cortex-M85 combined with Ethos-U85 platform has improved machine learning (ML) computing performance by eight times, bringing significant breakthroughs in AI computing power and empowering edge AI devices to easily run large models with over 1 billion parameters.

Image: Arm edge AI computing platform supports running end-to-end AI models with over 1 billion parameters
Among them, the newly released ultra high energy efficiency Cortex-A320 not only provides higher memory capacity and bandwidth for Ethos-U85, making the execution of large models on Ethos-U85 more powerful, but also supports larger addressable memory space and can more flexibly manage multi-level memory access latency. The combination of Cortex-A320 and Ethos-U85 is an ideal choice for running large models and addressing the memory capacity and bandwidth challenges brought by edge AI tasks.
In addition, Cortex-A320 fully utilizes the AI computing features enhanced by Armv9, as well as security features including Secure EL2, Pointer Validation/Branch Object Recognition (PACBTI), and Memory Tag Extension (MTE). Previously, these features have been widely applied in other markets, and Arm has now introduced them into the field of IoT and edge AI computing, providing excellent and flexible AI performance while achieving better isolation of software loads and protection against software memory anomalies, improving overall system security.
The development of storage in the AI era: a comprehensive upgrade of storage, computing, and security capabilities
With the continuous growth of AI computing demand, cloud edge devices have put forward higher requirements for computing power, as well as more stringent requirements for storage system performance, density, real-time performance, and power consumption. In traditional models, computing architectures often separate storage and computation, with storage devices only playing the role of data storage. Data needs to be frequently moved between storage and computing nodes, resulting in a bottleneck between storage and computation. However, in the era of AI, in order to meet the needs of real-time data analysis, intelligent management, and efficient access, it has become particularly crucial to place storage closer to computing units or to enable the storage itself to have computing power. This ensures that AI tasks are efficiently executed in the most suitable location.
The requirements for storage throughput, latency, energy consumption, security, and improving host manageability such as Open Channel vary from cloud to end-to-end AI computing. The storage controller and firmware running on the Arm CPU in the storage controller play an extremely important role in supporting differentiated AI storage requirements.

Image: Arm’s rich IP platform solutions provide leading performance and energy efficiency for AI storage
In fact, as the cornerstone of data storage and network control, Arm has been providing high-performance, low-power, secure and reliable solutions for global storage controllers and devices, including:
The Arm Cortex-R series real-time processors have the fastest interrupt latency and real-time response speed, and are widely used in many storage devices;
The Arm Cortex-M series embedded processors are a popular choice for backend flash and media control, and support custom instructions. Customers can create differentiation through deep optimization for unique NAND media;
The Arm Cortex-A series application processors are designed with a high-throughput pipeline, supporting the highest processing performance, and have solid ecological support for ML, data processing software, and rich operating systems;
The Arm Ethos-U AI accelerator supports native Transformer acceleration of 2048 MACs per second, which can help the storage controller itself become smarter;
In addition, there is a Neoverse tailored for data centers. We have begun to see innovative designs in CXL (Compute Express Link) that combine Arm Coherent Mesh Network (CMN) with Neoverse to achieve “compositional” memory expansion and incorporate the concept of near storage computing to reduce data handling.
Ecological collaboration, building the future of AI computing and storage
While focusing on providing leading technology and products, Arm is also committed to working together with ecosystem partners to promote the development of the storage industry. The Arm architecture based platform is widely adopted by industry-leading storage enterprises to optimize their storage solutions. For example, Solidigm’s latest 122TB PCIe SSD Solidigm? D5-P5336 significantly improves the energy efficiency, storage density, and performance of AI data centers. Its storage controller uses Arm Cortex-R CPU, effectively enhancing real-time read and write performance and latency certainty; Silicon Motion’s SM2508 main control chip for AI PCs adopts Arm Cortex-R8 and Cortex-M0, achieving breakthroughs in energy efficiency and data throughput. Its SM2264XT-AT is the industry’s first PCIe Gen4 main control chip for vehicles, which supports data access for mixed critical workloads through enhanced virtualization and can save 30% of energy consumption; The XP2300, ORCA 4836 and UNICIA 3836 SSDs built by Jiang Bolong based on the Arm Cortex-R CPU are widely used in AI PC, servers, cloud computing, distributed storage, edge computing and other application scenarios by virtue of their advantages of large capacity and high performance, to meet the local deployment requirements of AI technology.
In addition, in the local storage market, leading storage companies such as Dapu Microelectronics, Lianyun Technology, Yixin Technology, Tenfei, Deyi Microelectronics, and Yingren Technology have also widely adopted Arm technology to create SSD main control chips and device solutions.
So far, nearly 20 billion storage devices have been applied based on the Arm architecture and platform, including cloud and enterprise SSDs, vehicle SSDs, consumer SSDs, hard drives, and embedded flash devices. Currently, storage devices powered by Arm technology continue to maintain a daily shipment volume of approximately 3 million units.
With cutting-edge technological strength, rich ecological layout, and profound accumulation in the storage industry, Arm is continuing to lead technological innovation and empower the development of computing and storage in the AI era. Arm will also continue to work with partners to build a new future for computing and storage in the AI era through a secure and efficient Arm computing platform.
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